The present invention relates to an inspection method and an inspection apparatus to detect a pattern defect by comparing patterns, which should be identical, and judging a mismatching part as a defect. More particularly, the present invention relates to an inspection method and an inspection apparatus to detect a defect in repetitive patterns of such as in semiconductor wafers, photomasks, and liquid crystal display panels.
A fixed pattern is repetitively formed on a semiconductor wafer, a semiconductor memory photomask, and a liquid crystal display panel etc. Therefore a pattern defect is detected, currently, by capturing the optical image of the pattern and comparing it with adjacent patterns. If no difference is found between the two patterns in the comparison, the patterns are judged to be nondefective and if any difference is found, it is judged that one pattern is defective. As such an apparatus is generally called an appearance inspection apparatus, this term is also used here. In the following description, the semiconductor wafer appearance inspection apparatus, which inspects the patterns formed on a semiconductor wafer for a defect, is described as an example. The present invention, however, is not restricted to this apparatus, but can be applied to appearance inspection apparatuses for a semiconductor memory photomask and a liquid crystal display panel etc., and moreover, to any apparatus with a structure in which patterns, which should be identical, are compared for defect inspection.
The manufacture of a semiconductor device includes a great number of processes and it is important to be able to detect the occurrence of defects in the final and intermediate processes to feed back the result to the manufacturing process, from the standpoint of yield enhancement. Therefore, an appearance inspection apparatus is widely used to detect such a defect. FIG. 1 is a diagram that shows the rough structure of a semiconductor wafer appearance inspection apparatus. As shown in FIG. 1, the semiconductor wafer appearance inspection apparatus comprises an image generation section 1 that generates the image signal of the surface of a semiconductor wafer, a defect candidate detection section 2 that detects a part that has the possibility of being a defect (defect candidate) by converting the image signal into digital data and comparing the corresponding patterns, and an automatic defect classification (ADC) section 3 that analyzes and classifies defect candidates into killer defects (fatal defects) that affect the yield and non-killer defects that can be ignored.
The image generation section 1 comprises a stage 18 that holds a semiconductor wafer 19, an optical system 11 that generates the surface image of the semiconductor wafer 19, and a control unit 20. The optical system 11 comprises a light source 12, illuminating lenses 13 and 14 that converge the illuminating light from the light source 12, a beam splitter 15 that reflects the illuminating light, an objective lens 16 that irradiates the illuminating light onto the surface of the semiconductor wafer 19 and at the same time projects the optical image of the surface of the semiconductor wafer 19, and an image pickup device 17 that converts the projected optical image of the surface of the semiconductor wafer 19 into the electrical image signal. As for the image pickup device 17, a TV camera employing two-dimensional CCD elements can be used, but in most cases, a line sensor, such as a one-dimensional CCD or TDI sensor, is used to obtain the image signal at a high resolution and images are captured by relatively moving (scanning) the semiconductor wafer 19 using the stage 18. Therefore, if optical images are captured by the line sensor while moving the semiconductor wafer 19 in the direction of the repetitive arrangement of patterns, the image signal of the same part of the pattern is eventually generated at fixed periods. Since the structure of the image generation section 1 is widely known, a fuller description is not given here.
The defect candidate detection section 2 comprises an analog-digital converter (A/D) 21 that converts the image signal put out from the image pickup device 17 into multivalued digital image data and a double detection circuit 22 that processes the digital image data, compares the same part of the pattern, and detects a defect candidate. The process in the defect candidate detection section 2 will be described later.
The ADC 3 analyzes the digital image data of the part of a defect candidate reported from the defect candidate detection section 2 and classifies the defect candidate.
Next the process in the double detection circuit 22 is further described. As described above, plural semiconductor chips (dies) are formed on the semiconductor wafer so as to be regularly arranged. The pattern of each die is identical because the same mask pattern is exposed. Therefore, the same pattern is repeated with pitches of the die arrangement as shown in FIG. 2A, and a comparison between two adjacent dies can be made. Such a comparison is called a die-die comparison. If there is no defect, the pattern coincides with each other, but a difference is found in the comparison result if a defect exists. When there exists a difference, however, it cannot be determined as to which one of the two dies is defective by the one-time comparison. Then, the comparison is made, twice, with the dies on both sides of each die as shown in FIG. 2A, and the part is judged to be non-defective if there is no difference in the two-time comparison and the part is judged to be defective if there exist a difference in each comparison of the two-time comparison. This method of judgment with the two-time comparison is called the double detection. The method of judgment with the one-time comparison is called the single detection. In either case, both methods of defect judgment, in which a comparison is made between two adjacent patterns, are based on a premise that the occurrence frequency of defects is comparatively low and that there is little possibility of the existence of defects on the same part of a pattern at the same time. In fact the occurrence frequency of fatal defects in patterns formed on a semiconductor wafer is very low in the manufacturing process and, therefore, such a premise does not lead to any problem.
As described above, the semiconductor wafer 19 is scanned by the optical system 11 that comprises the line sensor 17, and the image data corresponding to the scan width is generated sequentially as the scanning time elapses. Therefore, when the double detection is carried out, the image of die A is delayed by a repetition period and compared with that of die B sequentially and then, similarly, the image of die B is delayed by a repetition period and compared with that of die C sequentially, and the double detection process of die B is completed, as shown in FIG. 2A. Similarly, the double detection process is repeated for dies C, D, . . . , until the process is completed for all dies. Although the process for the first die A is the single detection process, it is effective because die B has been inspected and a mismatching part between die A and die B can be judged to be defective or not, but it is also applicable to compare die A with another die. The image data of the die for which the two-time comparison has been made can be deleted sequentially, and if it is designed so that the image data of the next die can be stored in the part of memory from which the previous data has been deleted, the memory capacity is sufficient if it can store the full image data of a die. In other words, the memory in this case functions as a delay memory that delays the image data by a repetition period. It is also applicable to provide a memory with a capacity large enough for the image data of all dies of a semiconductor wafer. In this case, an enormous memory capacity is required, but it is no longer necessary to generate the image data again by scanning the semiconductor wafer for the analysis of the defective part in the ADC 3.
A unit pattern called a cell is arranged repeatedly at fixed periods in the arrangement part of the memory cells of the semiconductor memory. In such a part, a comparison between cells can be made, and such a comparison is called the cell-cell-comparison. FIG. 2B shows the cell-cell-comparison and the double detection process is sequentially carried out between two adjacent cells among cells P-S in the same manner as the die-die comparison.
The double detection process needs to be performed in synchronization with generation of image data and a very high speed processing ability is required. Although a circuit to perform such a process can be realized by a structure that combines a delay memory and a comparison circuit, in most cases it is realized by a structure that combines a pipeline data processing processor and a working memory, because it is difficult to adjust comparison positions and make the repetition period variable.
FIG. 3 is a flow chart that shows the defect candidate detection process of the defect candidate detection section 2. Digitized multivalued (gray level) image data 100, which is put out sequentially from the A/D 21, is delayed by an amount of time corresponding to a repetition period (die arrangement pitch in the die-die comparison, or cell arrangement pitch in the cell-cell comparison) in step 101. This process corresponds to a process to access and read the previous gray level image data by a repetition period stored sequentially in the working memory. In step 102, a differential image is generated by operating the difference between the gray level image data and that delayed by a period, that is, the difference between the two gray level image data separated from each other by an arrangement pitch. The operation in this case is an operation to calculate the absolute value of the difference in the gray level image data that does not relate to the polarity, therefore the obtained differential image is also the data that does not relate to the polarity.
In step 103, the differential image is compared with a fixed threshold value to detect the part at which the value of the differential image is greater than the threshold value. In other words, the part at which the difference between two gray level image data is great is detected in this process. In this manner, a two-valued one-time judged image 104 can be obtained. That is, the one-time judged image 104 is the result of the single detection process.
In step 105, the one-time judged image 104 is further delayed by a period. During this, the above-mentioned steps are performed to obtain the next one-time judged image 104 and the AND operation is performed in step 106 between the one-time judged image 104 delayed by a period and that which is not delayed. In this manner, a two-time judged image 107 that indicates the part where the difference is great in both comparisons can be obtained. That is, the two-time judged image 107 is the result of the double detection process and is a defect candidate image.
For the semiconductor wafer appearance inspection apparatus, it is essential to be able to detect every part that includes a difference without fail, therefore, it is designed so as to recognize the part as a defect, at which the difference between the two images exceeds a fixed threshold value, as described above. Therefore, the number of the parts judged to be a defect candidate depends considerably on the specified threshold value. As described above, the part judged to be a defect candidate is reported to the ADC 3 and analyzed again whether it is a fatal defect (killer defect) that affects the yield of the semiconductor device. A problem, however, is caused that the time required for analysis increases as the number of the defect candidates increases and the throughput is degraded, because the pipeline processing of this part is difficult and a considerable time is required for the analysis of a part. Therefore, it is preferable that the double detection circuit 22 detects every killer defect as a defect candidate without fail but detects as few non-killer defects as possible.
There exists, however, another problem that it is difficult to meet the demand only with the setting of the threshold value because the part at which the difference between two images is great is not always a killer defect. In the metal process of the semiconductor device, for example, the killer defect that users want to detect is a short between patterns and it will be preferable if a non-killer defect such as a metal grain is left out of defect candidates. In many cases, however, the difference in gray level resulted from the metal grain is by far greater than that resulted from the part of a short between patterns. Therefore, if the threshold is set to a value so that the metal grain is not detected at all as a defect candidate, a short between patterns, which should be primarily detected, is seldom detected. As a result, a threshold is set to a value so that a short between patterns is detected without fail, with not only a short and but also a metal grain being detected temporarily as a defect candidate, and the ADC 3 classifies them according to whether they are killer defects or not.
Conventionally, the ADC 3 is not provided and the classification is performed by a visual inspection of each defect candidate that is moved again to the stage of a microscope using an appearance inspection apparatus or another apparatus called the review station, therefore, an enormous time is required for classification when there exist many metal grains. Recently, the trend is beginning to appear that the ADC 3 is employed for automatic classification but, for the automatic classification, the image of the die that includes the detected defect candidate and at least one of the die images used in the comparison are needed, and it is necessary to obtain these images again, send them to the ADC 3, and detect the defect candidates again before the classification of the defects. If a memory with a capacity large enough to store image data of all dies of a single semiconductor wafer is provided, as described above, it is no longer necessary to obtain image data of the semiconductor wafer again for analysis of defective parts in the ADC 3, but the memory capacity required for image data of all dies is tremendously large, resulting in considerable increase in cost.
As described above, the double detection circuit performs the comparison process at a speed as high as, for example, 1 G pixel/second, in order to realize a high throughput, therefore, this part forms a considerable proportion of the cost of the appearance inspection apparatus. In other words, it can be said that the cost of the apparatus and the throughput thereof are in an inverse relation, and the processing performance of the double detection circuit (a pipeline data processing processor and a memory) had to be specified, various factors being taken into consideration. As a result, for example, an upper limit was set to the number of defect candidates that can be reported per unit processed image, and when the number of detected defect candidates exceeds the upper limit, it is reported that a single large defect exists in the unit processed image. As described above, it causes a problem that a tremendous cost and processing time are required to send the two image data relating to all the detected defect candidates to the automatic defect classification (ADC) section and detect again the defect candidates among all the defect candidates for classification in the ADC.